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專利授權區
專利名稱(中)	半導體功率元件及其製造方法
專利名稱(英)	SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF
專利家族	中華民國：I918430
專利權人	國立清華大學 100.00%
發明人	黃敬源
技術領域	能源科技,電子電機

專利摘要(中)
一種半導體功率元件及其製造方法。所述半導體功率元件包括基底、緩衝層、氮化物通道層、源極、汲極、阻障層、第一蝕刻停止層、第一鈍化層、第二蝕刻停止層、第二鈍化層、閘極結構、間隙壁以及場板結構。所述緩衝層設置於所述基底上。所述氮化物通道層設置於所述緩衝層上。所述源極與所述汲極設置於所述氮化物通道層上。所述阻障層設置於所述源極與所述汲極之間的所述氮化物通道層上。所述第一蝕刻停止層設置於所述阻障層、所述源極與所述汲極上。所述第一鈍化層設置於所述第一蝕刻停止層上。所述第二蝕刻停止層設置於所述第一鈍化層上。所述第二鈍化層設置於所述第二蝕刻停止層上。所述閘極結構設置於所述第二鈍化層、所述第二蝕刻停止層與所述第一鈍化層中。所述間隙壁設置於所述閘極結構與所述第二鈍化層以及所述第二蝕刻停止層之間。所述場板結構設置於所述第二鈍化層中。二維電子氣位於所述源極與所述汲極之間的所述氮化物通道層中，且鄰近所述氮化物通道層與所述阻障層之間的界面。

專利摘要(中)

一種半導體功率元件及其製造方法。所述半導體功率元件包括基底、緩衝層、氮化物通道層、源極、汲極、阻障層、第一蝕刻停止層、第一鈍化層、第二蝕刻停止層、第二鈍化層、閘極結構、間隙壁以及場板結構。所述緩衝層設置於所述基底上。所述氮化物通道層設置於所述緩衝層上。所述源極與所述汲極設置於所述氮化物通道層上。所述阻障層設置於所述源極與所述汲極之間的所述氮化物通道層上。所述第一蝕刻停止層設置於所述阻障層、所述源極與所述汲極上。所述第一鈍化層設置於所述第一蝕刻停止層上。所述第二蝕刻停止層設置於所述第一鈍化層上。所述第二鈍化層設置於所述第二蝕刻停止層上。所述閘極結構設置於所述第二鈍化層、所述第二蝕刻停止層與所述第一鈍化層中。所述間隙壁設置於所述閘極結構與所述第二鈍化層以及所述第二蝕刻停止層之間。所述場板結構設置於所述第二鈍化層中。二維電子氣位於所述源極與所述汲極之間的所述氮化物通道層中，且鄰近所述氮化物通道層與所述阻障層之間的界面。

專利摘要(英)
A semiconductor power device and a manufacturing method thereof are provided. The semiconductor power device includes a substrate, a buffer layer, a nitride channel layer, a source, a drain, a barrier layer, a first etching stop layer, a first passivation layer, a second etching stop layer, a second passivation layer, a gate structure, a spacer, and a field plate structure. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The source and the drain are disposed on the nitride channel layer. The barrier layer is disposed on the nitride channel layer between the source and the drain. The first etching stop layer is disposed on the barrier layer, the source and the drain. The first passivation layer is disposed on the first etching stop layer. The second etching stop layer is disposed on the first passivation layer. The second passivation layer is disposed on the second etching stop layer. The gate structure is disposed in the second passivation layer, the second etching stop layer and the first passivation layer. The spacer is disposed between the gate structure and the second passivation layer and the second etching stop layer. The field plate structure is disposed in the second passivation layer. A two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and is adjacent to an interface between the nitride channel layer and the barrier layer.

專利摘要(英)

A semiconductor power device and a manufacturing method thereof are provided. The semiconductor power device includes a substrate, a buffer layer, a nitride channel layer, a source, a drain, a barrier layer, a first etching stop layer, a first passivation layer, a second etching stop layer, a second passivation layer, a gate structure, a spacer, and a field plate structure. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The source and the drain are disposed on the nitride channel layer. The barrier layer is disposed on the nitride channel layer between the source and the drain. The first etching stop layer is disposed on the barrier layer, the source and the drain. The first passivation layer is disposed on the first etching stop layer. The second etching stop layer is disposed on the first passivation layer. The second passivation layer is disposed on the second etching stop layer. The gate structure is disposed in the second passivation layer, the second etching stop layer and the first passivation layer. The spacer is disposed between the gate structure and the second passivation layer and the second etching stop layer. The field plate structure is disposed in the second passivation layer. A two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and is adjacent to an interface between the nitride channel layer and the barrier layer.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw