| 專利名稱(英) | Apparatus of Three-Dimensional Integrated-Circuit Chip Using Fault-Tolerant Test Through-Silicon-Via |
| 專利家族 |
美國:9,304,167 |
| 專利權人 | 國立清華大學 100.00% |
| 發明人 | 陳福偉,黃婷婷 |
| 技術領域 | 資訊工程,電子電機 |
| An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip. |
| 承辦人姓名 | 李曉琪 |
| 承辦人電話 | 03-5715131 #31061 |
| 承辦人Email | hsiaochi@mx.nthu.edu.tw |