A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells. |