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專利授權區
專利名稱(英)	Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
專利家族	中華民國：I292541 美國：7,302,655
專利權人	國立清華大學 100%
發明人	謝禎安,吳世傑,王俊堯
技術領域	電子電機

專利摘要(中)
A method for verifying a circuit design includes a step of assigning numerical values 1/a.sub.i to input ports of the circuit design according to a function a.sub.i＋1=(a.sub.i-1).sup.2＋1, wherein i represents the number of the input port and the numerical value a.sub.1 is not equal to 2 or 1. Preferably, a.sub.1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l’s probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.

專利摘要(中)

A method for verifying a circuit design includes a step of assigning numerical values 1/a.sub.i to input ports of the circuit design according to a function a.sub.i＋1=(a.sub.i-1).sup.2＋1, wherein i represents the number of the input port and the numerical value a.sub.1 is not equal to 2 or 1. Preferably, a.sub.1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l’s probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.

專利摘要(英)
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聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw