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專利授權區

專利授權區
專利名稱(英)	MEMORY STRUCTURE WITH INPUT-AWARE MAXIMUM MULTIPLY-AND-ACCUMULATE VALUE ZONE PREDICTION FOR COMPUTING-IN-MEMORY APPLICATIONS AND OPERATING METHOD THEREOF
專利家族	美國：11,416,146
專利權人	國立清華大學 100%
發明人	張孟凡,蘇建維,洪哲民,張傳佳,吳秉駿,任晉陞
技術領域	電子電機

專利摘要(英)
A memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications includes a memory array, an input-aware zone prediction circuit and an analog-to-digital converter. An input-aware maximum partial multiply-and-accumulate value voltage generator is configured to generate a maximum partial multiply-and-accumulate value according to at least one input value. A prediction-aware global reference voltage generator is configured to generate a plurality of global reference voltages, a maximum reference voltage and a selected minimum reference voltage. A maximum partial multiply-and-accumulate value zone detector is configured to generate a zone switch signal by comparing the maximum partial multiply-and-accumulate value and the global reference voltages. The analog-to-digital converter is configured to convert an analog multiply-and-accumulate output value of the memory array to a digital multiply-and-accumulate output value according to the maximum reference voltage, the selected minimum reference voltage and the zone switch signal.

專利摘要(英)

A memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications includes a memory array, an input-aware zone prediction circuit and an analog-to-digital converter. An input-aware maximum partial multiply-and-accumulate value voltage generator is configured to generate a maximum partial multiply-and-accumulate value according to at least one input value. A prediction-aware global reference voltage generator is configured to generate a plurality of global reference voltages, a maximum reference voltage and a selected minimum reference voltage. A maximum partial multiply-and-accumulate value zone detector is configured to generate a zone switch signal by comparing the maximum partial multiply-and-accumulate value and the global reference voltages. The analog-to-digital converter is configured to convert an analog multiply-and-accumulate output value of the memory array to a digital multiply-and-accumulate output value according to the maximum reference voltage, the selected minimum reference voltage and the zone switch signal.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw