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專利授權區
專利名稱(中)	位元串列運算裝置與測試方法
專利名稱(英)	BIT-SERIAL COMPUTING DEVICE AND TEST METHOD FOR EVALUATING THE SAME
專利家族	PCT：WO2023138656A1(公開號) 中華民國：I839079 大陸：CN118556224A(公開號) 美國：2023-0236797(公開號)
專利權人	國立清華大學 100.00%
發明人	蔡喻至,丁文謙,呂仁碩
技術領域	資訊工程,電子電機

專利摘要(中)
一種位元串列運算裝置包含運算電路與一倍率乘法器。運算電路包括N個乘法累加電路片，每一乘法累加電路片計算輸入乘數向量與另一向量的一內積，另一向量由饋入被乘數向量的該等被乘數輸入中具有與該乘法累加電路片對應的權重之該等被乘數片段構成。倍率乘法器耦接到該等乘法累加電路片以接收等乘法累加電路片分別計算的該等內積，並且還接收第一控制信號。針對每一乘法累加電路片，倍率乘法器根據第一控制信號將該乘法累加電路片計算的內積乘上一加權比，以得出對應乘法累加電路片的倍率乘法後內積，加權比表示與乘法累加電路片對應的權重。

專利摘要(中)

一種位元串列運算裝置包含運算電路與一倍率乘法器。運算電路包括N個乘法累加電路片，每一乘法累加電路片計算輸入乘數向量與另一向量的一內積，另一向量由饋入被乘數向量的該等被乘數輸入中具有與該乘法累加電路片對應的權重之該等被乘數片段構成。倍率乘法器耦接到該等乘法累加電路片以接收等乘法累加電路片分別計算的該等內積，並且還接收第一控制信號。針對每一乘法累加電路片，倍率乘法器根據第一控制信號將該乘法累加電路片計算的內積乘上一加權比，以得出對應乘法累加電路片的倍率乘法後內積，加權比表示與乘法累加電路片對應的權重。

專利摘要(英)
A bit-serial computing device includes a computing circuit and a scaler. The computing circuit includes multiple MAC slices, and receives a multiplier vector and a multiplicand vector that contains multiple multiplicand inputs. Each multiplicand input contains multiple multiplicand segments that have different significances. The significances respectively correspond to the MAC slices. Correspondence between the significances and the MAC slices is variable. Each MAC slice calculates an inner product of the multiplier vector and a vector that is constituted by the multiplicand segments of the multiplicand inputs having the significance corresponding to the MAC slice. With respect to each MAC slice, the scaler multiplies the inner product that is calculated by the MAC slice by a weighting ratio that represents the significance corresponding to the MAC slice, so as to obtain a scaled inner product that corresponds to the MAC slice.

專利摘要(英)

A bit-serial computing device includes a computing circuit and a scaler. The computing circuit includes multiple MAC slices, and receives a multiplier vector and a multiplicand vector that contains multiple multiplicand inputs. Each multiplicand input contains multiple multiplicand segments that have different significances. The significances respectively correspond to the MAC slices. Correspondence between the significances and the MAC slices is variable. Each MAC slice calculates an inner product of the multiplier vector and a vector that is constituted by the multiplicand segments of the multiplicand inputs having the significance corresponding to the MAC slice. With respect to each MAC slice, the scaler multiplies the inner product that is calculated by the MAC slice by a weighting ratio that represents the significance corresponding to the MAC slice, so as to obtain a scaled inner product that corresponds to the MAC slice.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw