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專利授權區
專利名稱(中)	在線監測時脈信號的電子電路
專利名稱(英)	ELECTRONIC CIRCUIT FOR ONLINE MONITORING A CLOCK SIGNAL
專利家族	中華民國：I728920 美國：11,287,471
專利權人	國立清華大學 100.00%
發明人	黃錫瑜,陳韋豪,許竹均
技術領域	能源科技

專利摘要(中)
本發明提供一種用於在線監測時脈信號的電子電路。電子電路包含週期至脈衝轉換器、脈衝縮減區塊以及編碼器。週期至脈衝轉換器接收時脈信號，且轉換時脈信號的多個時脈週期樣本中的每一者以生成具有多個脈衝的脈衝串信號。脈衝縮減區塊接收脈衝串信號的多個脈衝，且藉由縮減脈衝串信號的多個脈衝來生成多個捕獲位元。編碼器根據多個捕獲位元來輸出最小編碼及最大編碼，最小編碼指示時脈信號的最小時脈週期，最大編碼指示時脈信號的最大時脈週期。電子電路減去最大編碼及最小編碼以生成峰對峰抖動量編碼。

專利摘要(中)

本發明提供一種用於在線監測時脈信號的電子電路。電子電路包含週期至脈衝轉換器、脈衝縮減區塊以及編碼器。週期至脈衝轉換器接收時脈信號，且轉換時脈信號的多個時脈週期樣本中的每一者以生成具有多個脈衝的脈衝串信號。脈衝縮減區塊接收脈衝串信號的多個脈衝，且藉由縮減脈衝串信號的多個脈衝來生成多個捕獲位元。編碼器根據多個捕獲位元來輸出最小編碼及最大編碼，最小編碼指示時脈信號的最小時脈週期，最大編碼指示時脈信號的最大時脈週期。電子電路減去最大編碼及最小編碼以生成峰對峰抖動量編碼。

專利摘要(英)
An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

專利摘要(英)

An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

聯絡資訊
承辦人姓名	李曉琪
承辦人電話	03-5715131 #31061
承辦人Email	hsiaochi@mx.nthu.edu.tw