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專利授權區


專利授權區
專利名稱(英) MEMORY UNIT WITH TIME DOMAIN EDGE DELAY ACCUMULATION FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF
專利家族 美國:11,967,357
專利權人 國立清華大學 100% ,國立清華大學 100%
發明人 張孟凡,吳秉駿,洪立洋,任晉陞,蘇建維
技術領域 電子電機
專利摘要(英)
A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.
聯絡資訊
承辦人姓名 李曉琪
承辦人電話 03-5715131 #31061
承辦人Email hsiaochi@mx.nthu.edu.tw
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