![]() |
|
---|---|
專利名稱(英) | MULTI-BIT CURRENT SENSE AMPLIFIER WITH PIPELINE CURRENT SAMPLING OF RESISTIVE MEMORY ARRAY STRUCTURE AND SENSING METHOD THEREOF |
專利家族 |
美國:11,049,550 |
專利權人 | 國立清華大學 100.00% |
發明人 | 張彤誠,李俊穎,張孟凡 |
技術領域 | 電子電機 |
![]() |
---|
A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle. |
![]() |
---|
A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle. |
![]() |
|
---|---|
承辦人姓名 | 李曉琪 |
承辦人電話 | 03-5715131 #31061 |
承辦人Email | hsiaochi@mx.nthu.edu.tw |